ASIC Engineer Sr Staff

This role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from an HPE office.

Job Description:

About HPE Networking:

At HPE Networking, we are redefining the future of high-performance networking. Our silicon team is at the forefront of innovation, developing cutting-edge ASICs for next-generation networking platforms. We are looking for a seasoned

Design-for-Test (DFT) Engineer to join our team and contribute to the development of advanced 3nm and beyond networking silicon.

Job Summary:

As a DFT Engineer at HPE Networking, you will play a critical role in ensuring the testability and reliability of our high-speed, high-complexity ASICs. You will work closely with front-end design, physical design, and verification teams to architect and implement robust DFT solutions that meet stringent performance and quality requirements.

Key Responsibilities:

• Define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond.
• Collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features.
• Develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models.
• Analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations.
• Apply test constraints and perform STA analysis to ensure timing closure in test modes.
• Support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF).
• Conduct silicon failure analysis and contribute to system-level debug and yield improvement.
• Automate DFT flows and analysis using scripting languages such as Perl and Tcl.

Required Skills & Experience:

• 10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains.
• Deep understanding of fault models: stuck-at, transition, path-delay.
• Expertise in scan compression, ATPG, and MBIST architecture.
• Experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair.
• Proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler.
• Simulation experience with Synopsys VCS and Cadence NC-Verilog.
• Timing analysis using PrimeTime and Cadence Tempus.
• Able to define test constraints and review STA reports to ensure timing closure in test modes.
• Debugging with waveform tools such as Novas and SimVision.
• Familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF.
• Strong scripting skills in Perl and Tcl for automation and analysis.

Preferred Qualifications:

• Experience in silicon bring-up and system-level failure analysis for advanced process nodes (3nm and below).
• Familiarity with high-speed networking protocols and system-level test strategies.
• Exposure to yield analysis and production test optimization.

Why HPE Networking?

• Be part of a world-class silicon team driving innovation in networking.
• Work on industry-leading technologies at the bleeding edge of semiconductor design.
• Enjoy a collaborative, inclusive, and forward-thinking work environment.
• Competitive compensation, benefits, and career growth opportunities.

Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

#unitedstates

#networking

Job:

Engineering

Job Level:

TCP_05

States with Pay Range Requirement

The expected salary/wage range for a U.S.-based hire filling this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. If this is a sales role, then the listed salary range reflects combined base salary and target-level sales compensation pay. If this is a non-sales role, then the listed salary range reflects base salary only. Variable incentives may also be offered. Information about employee benefits offered can be found at https://myhperewards.com/main/new-hire-enrollment.html.

USD Annual Salary: $148,000.00 - $340,500.00

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.